The present invention generally relates to a dynamic random access memory, and more particularly to a dynamic random access memory having an improved layout. Further, the present invention is concerned with a method of arranging a memory cell pattern of the dynamic random access memory.
Recently, the layout of structural elements of a dynamic random access memory (hereinafter simply referred to as a DRAM) has been designed by using a computer. In order to reduce the amount of data to be processed, the layout is designed by using straight lines extending in two orthogonal directions and straight lines extending at an angle of 45.degree. with respect to each of the orthogonal directions. However, advanced computers has an ability to process an extremely large amount of data at high speeds and thus makes it possible to design the layout by using oblique lines which extend at angles other than 45.degree. with respect to the aforementioned orthogonal directions.
Referring to FIG. 1, there is illustrated a layout of a DRAM of a stacked capacitor type. In FIG. 1, AR indicates an active (diffusion) region including a drain region and a source region, a word line and S indicates a source area. D indicates a drain area. WL indicates a word line and WL' denotes the distance between the adjacent word lines WL. BL indicates a bit line and BL' indicates an extension portion of the bit line BL. BH indicates a bit line contact hole and SE indicates a storage electrode. SH indicates a storage electrode contact hole. GP is the space between the extension portion BL' of the bit line BL and the adjacent bit line BL.
FIG. 2 is a sectional view taken along line II-II shown in FIG. 1. A P-type silicon semiconductor substrate 1 has a source region S and drain region D of a transfer transistor, both of which are active regions (impurity diffused regions) buried in the Si substrate 1. A field insulating layer 2 and a gate insulating layer 3 are formed on the Si substrate 1. CP indicates an opposed electrode (cell plate) of a storage capacitor. The bit line BL is formed at a layer level lower than that of the opposed electrode CP. The word line WL' the bit line BL' the storage electrode SE and the opposed electrode CP are stacked in this order. A stacked capacitor is composed of the storage electrode SE, a dielectric film DE and the cell plate CP. This arrangement would become popular as the size of memory cells is further reduced.
In the arrangement shown in FIGS. 1 and 2, each bit line contact hole BH used for electrically coupling the bit line BL and the source region S of the transfer transistor must be positioned so that it keeps away from the word line WL. The storage electrode contact hole SH used for electrically coupling the storage electrode SE and the drain region D of the transfer transistor must be positioned so that it keeps away from both the word line WL and the bit line BL.
Each bit line BL must be provided with the extension portion BL' which is formed so that it surrounds the contact hole BH. The presence of the extension portion BL' increases the surface area of the bit line BL so that a parasitic capacitance is increased. In addition, the arrangement shown in FIGS. 1 and 2 causes short circuiting in the vicinity of the bit line extension portion BL', since the distance GP between the bit line extension portion BL' and the adjacent bit line BL is smaller than the distance between the adjacent bit lines BL.
Length DM of each memory cell measured in the direction in which each bit line BL extends is described as follows. ##EQU1## where a: half the width of the bit line contact hole BH
e: alignment margin of each of the contact holes PA1 d: the width of the word line WL PA1 c: half the width of the storage electrode contact hole SH PA1 WL' the distance between the adjacent word lines WL
It can be seen from FIG. 1 that A=a+e+d+e+c=a+c+d+2e. The bit line contact hole BL and the storage electrode contact hole SH are arranged approximately in a line so that the length DM of each memory cell is great.